The present invention generally relates to semiconductor integrated circuits and more particularly to a semiconductor integrated circuit of compound semiconductor devices formed on a semi-insulating compound semiconductor substrate.
Compound semiconductor materials such as gallium arsenide, aluminum arsenide, indium phosphide, indium arsenide and the like, are characterized by the high electron mobility and used for super-fast semiconductor devices such as MESFET (metal semiconductor field effect transistor), HEMT (high electron mobility transistor), HBT (heterojunction bipolar transistor) and the like. These semiconductor devices are generally used in the form of integrated circuits wherein a large number of semiconductor devices are assembled on a common substrate. In the integrated circuit of compound semiconductor devices, efforts are made to increase the integration density such that the operational speed of the device is increased further.
Generally, the integrated circuit of compound semiconductor devices uses a semi-insulating compound semiconductor substrate and semiconductor devices are formed thereon with a device isolation region formed therebetween for isolating the individual devices. This device isolation region may be a region of increased resistivity formed by doping impurities that form a deep impurity level in the compound semiconductor material or may be an isolation trench.
When the integration density is increased in such compound semiconductor integrated circuits, it is known that a so-called side gate effect appears wherein the device characteristic such as the threshold voltage of the device in the integrated circuit is changed or modified when a large negative voltage such as the power voltage is applied to an adjacent device in the same integrated circuit. This side gate effect becomes appreciable with increasing integration density and limits the integration density of the integrated circuit.
Various efforts are made in order to eliminate or minimize the side gate effect. FIG. 1, for example, shows the structure of a conventional integrated circuit that has succeeded in eliminating the side gate effect.
The device of FIG. 1 is constructed on a semi-insulating GaAs (gallium arsenide) substrate 1 and includes an undoped, insulating buffer layer of GaAs grown on the GaAs substrate 1 at a temperature of 200.degree. C. It should be noted that the GaAs layer thus grown at a low temperature lower than about 350.degree. C. has a deviation in composition from the ideal GaAs stoichiometry such that the content of As is slightly larger than Ga. Thereby, a large number of defects that cause the trapping of electrons are formed in the buffer layer 2 and the buffer layer 2 shows a large resistivity.
On the buffer layer 2, a second undoped GaAs buffer layer 3 is grown at a temperature of 680.degree. C., and on this second buffer layer 3, the active semiconductor devices are formed. In the illustrated example, the active devices form the HEMT and each device includes an undoped GaAs active layer 4 grown on the buffer layer 3 at 680.degree. C., an electron supplying layer 5 of n-type AlGaAs grown epitaxially on the active layer 4 with the composition of Al.sub.0.3 Ga.sub.0.7 As, and a cap layer 6 of n-type GaAs grown epitaxially further on the electron supplying layer 5. As is well known, the electron supplying layer 5 and the active layer 4 form a heterojunction at an interface therebetween and there is formed a two-dimensional electron gas in the active layer 4 along the heterojunction.
The layers 4 through 6 are provided commonly to the devices in the integrated circuit, and the individual devices are isolated from each other by a device isolation region 11 that is formed by an ion implantation of oxygen such that the region 11 reaches the buffer layer 3.
After the formation of the device isolation region 11, source electrodes 12A, 12B, . . . and drain electrodes 13A, 13B, . . . are formed on the cap layer 6. Further, a part of the cap layer 6 corresponding to where the gate electrode is to be formed is removed selectively by etching, and gate electrodes 14A, 14B, . . are provided in correspondence to the recessed parts thus formed.
FIGS. 2A-2C show the temperature of growth used to form the structure of FIG. 1, the compositional deviation from the ideal GaAs stoichiometry in various parts of the structure of FIG. 1, and the number of defects in the structure of FIG. 1, respectively. In FIG. 2B, the deviation of the composition is represented in terms of the difference between the atomic percent of As and that of Ga in the GaAs layer and is supposed to be zero when the material of the layer has the ideal stoichiometry. As will be noted in these drawings, the GaAs buffer layer 2 grown at 200.degree. C. has a deviation in the stoichiometry that reaches as much as about 1 % in terms of the difference in the composition of Ga and As. Associated with this significant deviation in the stoichiometry, there appears a large number of defects in the layer 2 as shown in FIG. 2C. As already noted, such defects in the buffer layer 2 captures the electrons entering into the layer 2 and the layer 2 shows a high resistivity. With the high resistivity layer 2 thus incorporated, the device of FIG. 1 interrupts the leak current path formed between the GaAs substrate 1 and the buffer layer 3, and it is believed that this is the reason the integrated circuit of FIG. 1 is successful in eliminating the side gate effect.
FIG. 3 shows the characteristic of the integrated circuit of FIG. 1 measured at 300.degree. K. In this measurement, the drain current I.sub.D was measured for the HEMT 20A of FIG. 1. In this structure, it should be noted that the buffer layer 2 has a thickness of about 500.ANG., the buffer layer 3 has a thickness of about 5000.ANG., and the device isolation region 11 has a width of about 2 .mu.m. The drain current I.sub.D was measured as a function of time while applying a constant drain voltage VD of 1 volt to the drain electrode 13A and simultaneously applying a side gate voltage VG of -5 volts across the source electrode 12B and the drain electrode 13B of adjacent HEMT 20B. As can be seen from FIG. 3, the drain current I.sub.D of the device 20A is stable as long as the device is operated at 300.degree. K. and the side gate effect is satisfactorily eliminated.
The success of the structure of FIG. 1 suggests that the side gate effect is caused as a result of the flow of carriers that somehow enter into the device region of the HEMT 20A in response to the side gate voltage in the HEMT 20B or vice versa through the semi-insulating substrate 1. In the structure of FIG. 1, such a path of the carriers through the substrate 1 is interrupted by the buffer layer 2.
On the other hand, when the device is operated at a low temperature such as 85.degree. K., it was found that the drain current of the HEMT of FIG. 1 decreases exponentially with time when a side gate voltage is applied to the adjacent HEMT. FIG. 4 shows the result of experiment undertaken at 85.degree. K. for the same sample used for the experiment of FIG. 3, under the same experimental condition. The result of FIG. 4 clearly shows that the HEMT of FIG. 1 cannot eliminate the side gate effect when operated at such a low temperature. It should be noted that the electron mobility of the two-dimensional electron gas formed at the heterojunction interface between the layer 4 and the layer 5 and determines the operational speed of HEMT, increases significantly at low temperatures such as 85.degree. K. Therefore, the HEMT of FIG. 1 is potentially capable of exhibiting a performance that is far superior to the performance obtained at the room temperature when operated at low temperatures. Thus, the side gate effect of the device of FIG. 1 occurring at these low temperatures significantly diminishes the performance of the HEMT.
The side gate effect of the foregoing type appearing only at low temperatures is believed to be caused by the defects that are intentionally introduced into the GaAs buffer layer 2. More specifically, when the electrons in the buffer layer 3 are accelerated and entered into the buffer layer 2 as the hot electrons as shown in FIG. 5, these electrons are trapped by the defects in the layer 2. At the room temperature, these trapped electrons are released again in due course due to the thermal energy of the electrons and the accumulation of electrons in the buffer layer 2 does not occur. At the low temperatures such as 85.degree. K., on the other hand, the trapped electrons are no longer released. Thereby, the buffer layer 2 is charged electrically with time and modifies the potential level in the device. Anyway, the conventional HEMT of FIG. 1 could operate satisfactorily only at the room temperature and one cannot exploit the potentially superb performance of the device that is obtained at the low temperature.
Meanwhile, the inventors of the present invention have discovered, in a series of experiments conducted on the device of FIG. 1 and forming one of the basis of the present invention, that the transconductance of the HEMT decreases with increasing thickness of the buffer layer 2 and increases with increasing overall thickness of the buffer layers 2 and 3. FIGS. 6 and 7 show the relationship found by the inventors. As can be seen in FIG. 6, the transconductance remains at about 200 mA/mm as long as the thickness of the GaAs buffer layer 2 is smaller than about 1000.ANG. while decreases rapidly when the thickness exceeds 1000.ANG.. Referring to FIG. 7, on the other hand, the transconductance is smaller than 200 mA/mm when the overall thickness of the layers 2 and 3 is smaller than about 4000.ANG., while a value exceeding 200 mA/mm is obtained when the overall thickness is set about 4000.ANG. or larger. Thus, the relationship in FIGS. 6 and 7 imposes a certain limitation in the design of the HEMT when one attempts to eliminate the foregoing problem of the side gate effect.